Volume 1, Issue 3 (9-2009)                   IJICTR 2009, 1(3): 45-51 | Back to browse issues page

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Nasir Q, AI-Araji S. Performance Analysis of Zero Crossing DPLL with Linearized Phase Detector . IJICTR. 2009; 1 (3) :45-51
URL: http://ijict.itrc.ac.ir/article-1-285-en.html
1- Department of Electrical and Computer Engineering University of Sharjah Sharjah , UAE
2- Communication Engineering Department Khalifa University of Science, Technology and Research Sharjah , UAE
Abstract:   (1414 Views)

This work introduces a new structure of Zero Crossing Digital Phase Locked Loop with Arc Sine block (ASZCDPLL) to linearize the phase difference detection, and enhance the loop performance. The new loop has faster acquisition, less steady state phase error, and wider locking range as compared to the conventional ZCDPLL. The locking range improvement and faster acquisition have been confirmed through simulation. The loop has been implemented and tested in real time using Texas Instruments TMS320C6416 DSP development kit.

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Type of Study: Research | Subject: Communication Technology

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