TY - JOUR T1 - Performance Analysis of Zero Crossing DPLL with Linearized Phase Detector TT - JF - ITRC JO - ITRC VL - 1 IS - 3 UR - http://ijict.itrc.ac.ir/article-1-285-en.html Y1 - 2009 SP - 45 EP - 51 KW - non-uniform sampling KW - digital phase locked loops KW - zero crossing DPLL N2 - This work introduces a new structure of Zero Crossing Digital Phase Locked Loop with Arc Sine block (ASZCDPLL) to linearize the phase difference detection, and enhance the loop performance. The new loop has faster acquisition, less steady state phase error, and wider locking range as compared to the conventional ZCDPLL. The locking range improvement and faster acquisition have been confirmed through simulation. The loop has been implemented and tested in real time using Texas Instruments TMS320C6416 DSP development kit. M3 ER -