ARTEMIS: A Simulator Tool for Heterogeneous Network-on-Chip
Complex homogeneous network-on-chip or heterogeneous network-on-chip increases the need of determining and developing simulation tools for designer to evaluate and comparison network performance. Towards this end, ARTEMIS tool, a matlab based simulator environment is developed. This simulator offers some collections of network configuration regarding to the topology graph, routing algorithm and switching strategy, including allocation scheme for a target application. Consequently, designers can choose the number and depth of virtual channels and the capacity of each link by applying an efficient allocation scheme, which is provided by this tool. Average latency and throughput are evaluation performance metrics that are measured with proposed simulator tool.
 J. Hu and R. Marculescu, Application-specific buffer space allocation for networks-on-chip router design, IEEE/ACM International Conference on Computer Aided Design (2004), 354-361.
 P. Abad, P. Prieto, L. Menezo, A. Colaso, V. Puente, and J. A. Gregorio, Topaz: An open-source interconnection network simulator for chip multiprocessors and supercomputers, Sixth IEEE/ACM International Symposium on In Networks on Chip (2012), 99-106.
 N. Agarwal, T. Krishna, L. S. Peh, and N. Jha, Garnet: A detailed on-chip network model inside a full system simulator, IEEE International Symposium on Performance Analysis of Systems and Software (2009), 33- 42.
 N. Jiang, D. Becker, G. Michelogiannakis, J. Balfour, B. Towles, D. Shaw, J. Kim, and W. Dally, A detailed and flexible cycle-accurate network-on-chip simulator, In IEEE International Symposium on Performance Analysis of Systems and Software ( 2013), 86- 96.
 A. T. Tran and B. Baas, NoCTweak: a highly parameterizable simulator for early exploration of performance and energy of networks on-chip, Technical Report, VLSI Computation Lab, ECE Department, UC, University of California, Davis, [online] http://www.ece.ucdavis.edu/vcl/pubs/2012.07.techreport.noctweak/ (2012).
  M. Palesi, D. Patti and F. Fazzino, NOXIM released software (2005- 2010). [online] http://noxim.sourceforge.net.
 V. Puente, J. A. Gregorio, and R. Beivide, SICOSYS: an integrated framework for studying interconnection network performance in multiprocessor multiprocessor systems. Proceedings of the 10th Euromicro conference on Parallel, distributed and network-based processing (2002), 15-22.
 Y. Ben-Itzhak, E. Zahavi, I. Cidon, and A. Kolodny, HNOCS: Modular Open-Source Simulator for Heterogeneous NoCs, International Conference on Embedded Computer Systems (2012), 51-57.
 Z. Guz, I. Walter, E. Bolotin, I. Cidon, R. Ginosar, and A. Kolodny, Network delays and link capacities in application-specific wormhole NoCs, VLSI Design( 2007).
 T. Huang, U. Ogras, and R. Marculescu, Virtual channels planning for networks-on-chip, the 8th International Symposium on Quality Electronic Design (2007), 879- 884.
 A. Kahng, B. Lin, K. Samadi, and R. Ramanujam, Trace-driven optimization of networks-on-chip configurations, In Design Automation Conference (DAC), 47th ACM/IEEE (2010), 437- 442.
 M. Al Faruque and J. Henkel, Minimizing Virtual Channel Buffer for Routers in On-Chip Communication Architectures,
Proceedings Design, Automation and Test in Europe (2008), 1238-1243.
 M. Kreutz, C. Marcon, L. Carro, F. Wagner, and A. Susin, Design space exploration comparing homogeneous and heterogeneous network-on-chip architectures, Proceedings of the 18th annual symposium on Integrated circuits and system design( 2005), 190- 195.
 A. Mishra, N. Vijaykrishnan, and C. Das, A case for heterogeneous on-chip interconnects for CMPs, Proceedings of the 38th annual international symposium on Computer architecture (2011), 389- 400.
 A. Bakhoda, J. Kim, and T. Aamodt, Throughput-effective on-chip networks for many node accelerators, Proceedings of the 43rd Annual IEEE/ACM International Symposium on Micro architecture (2010), 421- 432.
 Y. Ben-Itzhak, I. Cidon, and A. Kolodny, Delay analysis of wormhole based heterogeneous NoC, Proceedings of the 5th ACM/IEEE international symposium on Networks-on- Chip (2011), 16- 168.
 P. P. Panda, C. Grecu, M. Jones, and A. Ivanov, Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures, IEEE Transactions on Computers (2005), Vol. 54, No. 8, 1025-1040.
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